Devices with integrated circuits (ICs) have increased in complexity and functionality, those devices have required ever more dynamic ICs to meet the demands of those device users. IC design rules may be concerned with avoiding situations where the IC will enter a latch-up mode. Latch-up mode refers to the sudden appearance of a short circuit across a low-impedance pathway between nearby elements of an integrated circuit. IC structures which include four alternatingly-doped regions of semiconductor material may pose a risk of the IC entering into a latch-up mode. For instance, set of N-P-N-P doped regions placed side by side will create a P-N-P junction and an N-P-N junction capable of propelling electrical current in a single direction across the variously-doped regions. An electrical spike or similar event may cause the device to enter latch-up mode in such circumstances, and the electrical short from circuit latch-up may remain intact until the device is powered down.
Conventional IC design rules have attempted to mitigate the risk of latch-up events by specifying a minimum separation distance between two similarly-doped semiconductors across an oppositely-doped semiconductor. These design rules play an increasingly important role in limiting the chip scaling as IC structures continue to increase in complexity and density. Related concerns such as separation distance between terminals, parasitic resistance of semiconductor regions, etc., have further constrained options for preventing the circuit from entering a latch-up mode.